Process - the generation of the manufacturing process used to make the chip. Generally given in terms of the width of the narrowest wire; say "0.18u process"
Core - the single silicon chip which contains the logic circuitry to implement a CPU; it will also contain some L1 cache RAM, and some cores have L2 cache as well.
Die - a single physical piece of silicon.
Package - the cartridge or pinned ceramic block that you get when you buy a named processor ("P3/600EB", "Athlon 550"). This contains a core, and possibly (as in the case of the Athlon or some of the P3 series) some second-level cache chips.
Packaged - of dies, means they are embedded in plastic or ceramic rather than being mounted as bare silicon.
Write combining - means that multiple separate writes to the same area of memory will be done simultaneously.
Write allocation - means that, if you write to a cache line, the cache line is loaded into the cache in its entirety (so the next write to it will be faster).
Dispatcher - the core of a post-RISC chip. Works out in what order to execute parts of instructions in order to make the most efficient use of the hardware resources of a chip. In out-of-order chips, this may be different from the order the instructions appear in in the program; in-order chips keep the program flow as written, but might issue multiple independent consecutive instructions at once.
Pipe - something to which instructions can be issued by the dispatcher, to produce a result at some later time. A given pipe usually executes only one class of instructions ("integer instructions", "branches", "stores"), though the degree of specialism varies across chips from "all operations using the FP registers" down to "integer multiplication only".
Pipeline depth - modern chips consider several instructions simultaneously; a pipeline depth of 15 means that roughly 15 instructions per pipe are in flight (being handled at once). This is significant because an unpredicted branch requires the chip to discard all instructions in flight, so a deep pipeline makes unpredicted branches slow.
Superscalar - modern chips have multiple pipes of execution [say, two floating-point execute, two load-and-store floating-point, three integer ALU, a floating-point complex operation, two integer load, one integer store, two MMX ...]; three-way or three-issue superscalar means that three instructions may be dispatched, to different execution pipes, per cycle. "Superscalar floating point" implies simply that there is more than one floating-point pipe.
Pairing rules - if you wish to build a superscalar chip without having to design a complicated dispatcher (as in the Pentium generation when the technology wasn't up to fully superscalar x86 execution), one approach is to have rigid rules as to which sorts of instructions can be executed simultaneously. These are known as pairing rules.